General purpose microprocessor cores are known for implementation into integrated circuits for a wide variety of applications. Specialized computation engines which are specifically adapted to perform complex computational algorithms, such as Digital Signal Processing (DSP), are also known. DSP cores are specialized computation engines for carrying out digital signal processing tasks which are specially configured to efficiently process DSP algorithms. An example of a known DSP chip is the DSP 56002 processor, commercially available from Motorola. In order to achieve improved performance in DSP-related processing, the conventional approach is to combine a general purpose processor core together with a DSP core. The general purpose processor carries out Input/Output (I/O) tasks, logic functions, address generation, etc. This is a workable but costly solution. Additionally, evolving new applications require increasing amounts of memory and the use of multiple conventional digital signal processors. Additionally, power dissipation becomes a limiting factor in hardware of this type. The challenge, therefore, is to provide for improvements in processing performance while containing or reducing costs.
In view of the foregoing, one object of the present invention is to provide an improved computer architecture that utilizes available memory more efficiently in DSP and other specialized processor systems. Another object is to reduce the power consumption and size of computational processing systems.
A further object of the present invention is to provide for shared and reconfigurable memory in order to reduce I/O processor requirements in processor and co-processor architectures. A further object is to extend a shared, reconfigurable memory architecture to multiple memory blocks and execution units.
Another object of the present invention is to provide for microcode programming of a memory system controller in order to provide for dynamic reconfiguration of reconfigurable memory. A further object of the invention is to provide improvements in memory addressing methods, architectures and circuits for continuous execution together with simultaneous, continuous Direct Memory Access (DMA) operations.
A still further object of the invention is to provide improvements in execution units for computational operations, for example execution unit architectures that feature deep-pipeline structures and local registers, and that support parallel operations. Modified execution units can be used to improve efficiency of operation in conjunction with reconfigurable memory.
Yet another object of the present invention is a “virtual two port” memory structure based on a conventional, single-port memory cell. Yet another object is to provide for implementation in both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) configurations of the virtual two-port memory.